1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a fabrication method therefor. More particularly, the invention relates to a non-volatile semiconductor memory device having a logic circuit and a fabrication method therefor.
2. Description of the Related Art
A conventional fabrication method for a non-volatile semiconductor memory device, such as a flash memory, patterned a control gate in a memory cell area and a logic gate in a logic area using masks formed in separate lithography steps. This fabrication method is referred to as first prior art. In the present specification, a memory cell area includes an area reserved for the formation of memory cells or an area in which the formation of memory cells is under way, and a logic area includes an area reserved for the formation of a logic circuit or an area in which the formation of a logic circuit is under way.
Japanese Patent Laid-Open No. 193198/1995 discloses an improved fabrication method which reduces the number of steps in the fabrication method of the first prior art of forming a memory cell gate and a logic gate by patterning. The fabrication method described in this publication is referred to as second prior art.
Referring now to FIGS. 1 to 6, the fabrication method according to the second prior art will be discussed. FIGS. 1 to 6 are schematic cross-sectional views of the fabrication steps in the fabrication method for a non-volatile semiconductor memory device according to the second prior art and illustrate partial cross sections of the memory cell area and logic area of a non-volatile semiconductor memory device, which is undergoing a fabrication process or has substantially been completed, in the direction of the thickness of its substrate.
As shown in FIG. 1, silicon oxide films 102a and 102b are formed on a semiconductor substrate 101, such as p type silicon substrate. A first polysilicon layer 103, an ONO film 104, a second polysilicon layer 105 and a WSi film 106 are deposited on the silicon oxide film 102a in a memory cell area in the named order. Meanwhile, the second polysilicon layer 105 and the WSi film 106 are deposited on the silicon oxide film 102b in a logic area in the named order.
The silicon oxide film 102a is a film for forming the pattern of a tunnel film in the memory cell area. Also, the silicon oxide film 102b is a film for forming the pattern of a gate oxide film in the logic area. The first polysilicon layer 103 is used to form the pattern of a floating gate in the memory cell area. The ONO film is a laminated film with a three-layer structure having an SiO2 film, Si3N4 film and SiO2 film deposited in the named order. The second polysilicon layer 105 is used to form the pattern of a control gate in the memory cell area and the pattern of a logic gate in the logic area. Each of the first polysilicon layer 103 and the second polysilicon layer 105 may be an amorphous silicon layer.
The following is an example of approximate fabrication steps in the fabrication method of the second prior art until the cross section shown in FIG. 1 is formed. The silicon oxide film 102a is formed on the substrate 101. A polysilicon film is formed on the silicon oxide film 102a in the memory cell area and the logic area. Using a resist mask, the polysilicon film is removed from the logic area by etching and the polysilicon film in the memory cell is patterned to form the first polysilicon layer 103. An ONO film 104 is formed only in the memory cell area and the logic area. The ONO film 104 is left only in the memory cell area by etching and removing the ONO film 104 and the silicon oxide film 102a in the logic area using a resist mask on the memory cell area to expose the surface of the substrate 101 in the logic area. Then, the surface of the semiconductor substrate 101 in the logic area is oxidized to form a silicon oxide film 102b of a gate insulation film. Thereafter, the second polysilicon layer 105 and the WSi film 106 are formed in the memory cell area and the logic area in the named order.
Next, a thick silicon oxide film 111 and a resist film are deposited on the WSi film 106, and the resist film is patterned in both the memory cell area and the logic area to leave resist patterns 112a and 112b on the silicon oxide film 111, as shown in FIG. 2. Next, with the resist patterns 112a and 112b used as masks, the silicon oxide film 111, the WSi film 106 and the second polysilicon layer 105 in the memory cell area and the logic area are etched.
As shown in FIG. 3, a residual portion 105a of the second polysilicon layer, which is equivalent to the control gate, a residual portion 106a of the WSi film and a residual portion 111a of the silicon oxide film 111 are left deposited in the named order from the one closer to the ONO film 104 in the memory cell area after the etching. As shown in FIG. 3, a residual portion 105b of the second polysilicon layer 105, which is equivalent to the logic gate, a residual portion 106b of the WSi film 106 and a residual portion 111b of the silicon oxide film 111, are left laminated in the named order from the one closer to the silicon oxide film 102b, in the logic area after the etching.
Then, the resist patterns 112a and 112b are removed and the entire logic area is covered with a resist pattern 131 which is a new mask. In the state shown in FIG. 4, with the residual portion 111a of the thick silicon oxide film 111, which has already been patterned, used as a mask, the ONO film 104 in the memory cell area and the first polysilicon layer 103 to be a floating gate are etched.
FIG. 5 shows a cross section after the resist pattern 131 is removed after the etching step. Through the etching, a residual portion 103a of the first polysilicon layer 103, which is equivalent to the floating gate, and a residual portion 104a of the ONO film 104, which is equivalent to an intergate insulating layer, are left deposited in the named order from the one closer to the silicon oxide film 102a in the memory cell area after the etching. As shown in FIG. 5, the residual portion 111a of the silicon oxide film 111 used as a mask in the memory cell area is thinner than the one before the etching.
Thereafter, a flash memory as shown in FIG. 6 is formed by using a known method. In FIG. 6, a reference numeral “102a” constitutes a tunnel film, a reference numeral “102b” constitutes a gate oxide film. Also, a reference numeral “150” denotes a silicon oxide film side wall, reference numerals “151” and “153” denote sources, reference numerals “152” and “154” denote drains, a reference numeral “155” denotes a silicon oxide film, a reference numeral “156” denotes a contact and a reference numeral “157” denotes an interconnection.
However, the fabrication method of the first prior art has a shortcoming that the chip size should be increased in consideration of an alignment error. While the fabrication method of the second prior art can fabricate a memory device with a small memory cell size, it cannot silicide a gate once formed by patterning and is not suitable for a salicide process. Here, “salicide” is short for self-aligned silicide.
Referring to FIGS. 7 to 9, the following will discuss the reasons why the fabrication method of the first prior art and the fabrication method of the second prior art have the aforementioned shortcomings. FIG. 7 is a plan view of a part of a flash memory as seen from the direction perpendicular to the substrate. FIG. 8 is a plan view of a logic transistor in the logic area as seen from the direction perpendicular to the substrate. FIG. 9 is a partly cross-sectional view of the memory cell area in the thickness direction of the substrate, including the cross section of an insulating film formed along the side wall of the floating gate in the memory cell area.
In the fabrication method of the first prior art, the control gate in the memory cell area and the logic gate in the logic area are formed by separate etching steps using separate masks formed in separate lithography steps, so that contact holes to be formed in a subsequent step cannot be aligned with both gates. If the contact hole is aligned with the logic gate, it is necessary to provide a wide margin 161 between each contact and the control gate in FIG. 7. Specifically, as the logic gate and the control gate are aligned with a diffusion layer, a deviation for three lithography steps occurs between the control gate and the contact. Even if the deviation for a single lithography step is suppressed to a range of less than 0.05 μm, a maximum deviation of 0.15 μm may occur. This necessitates that the area should be widened for that deviation, resulting in a larger chip area. The same is applied to the case where contacts are aligned with the control gate.
In a general-purpose flash memory and a flash memory for filing, logic transistors to be mounted serve only to operate memory cells, so that the ratio of the area of the memory cells is large. Even if contacts are aligned with the control gate, using some of the transistor portion, therefore, the chip size does not become so large. Recently, large attention is paid to a logic-on-chip flash memory in which a logic with a sufficient function and a flash memory for storing programs are formed on a single chip. The adverse influence of an increase in the area caused by providing a misalignment margin is crucial to the logic-on-chip flash memory.
There has been some attempts to simultaneously form a control gate and a logic gate using a mask formed in a common lithography step as done in the fabrication method of the second prior art. This method however has the following problem. As shown in FIG. 9 which shows another cross section of a lamination type flash memory, as an insulating film (generally, an ONO film) between the control gate and the floating gate, an insulating film portion 181 is formed perpendicular to the substrate (not shown) on the side of the floating gate.
To sufficiently remove the insulating film portion 181 formed perpendicular to the side of the floating gate, the step of removing the resist mask on the control gate or the resist pattern 112a and then collectively etching the ONO film 104 and the first polysilicon layer 103 in the second prior art needs a sufficient time for etching the ONO film. In case where the insulating film portion formed perpendicular to the side of the floating gate is an ONO film with a thickness of 0.02 μm (200 Å), for example, there needs a time for etching the ONO film to the depth of 0.06 μm (600 Å) in the thickness direction.
Because the residual portion 111a of the silicon oxide film that becomes a mask on the control gate in that etching step has no selectivity with respect to the ONO film, a minimum thickness of 0.06 μm (600 Å) is required. Further, if the residual portion 111a of the silicon oxide film that serves as an etching mask is thin, the upper corners and sides of the control gate are etched. Preventing such etching requires that the silicon oxide film 111 for forming the residual portion 111a of the silicon oxide film that becomes a mask should be formed thick.
For example, the silicon oxide film 111 should have a thickness of 0.15 μm (1500 Å) or greater. The silicon oxide film 111 with a thickness of 0.15 μm (1500 Å) remains in the logic area as the residual portion 111b of the silicon oxide film 111 while keeping the original thickness. To silicide the logic gate, therefore, the residual portion 111b of the silicon oxide film should be etched.
In case of etching out the entire residual portion 111b of the silicon oxide film, however, the oxide film in a device isolation area is also etched to the depth of 0.15 μm (1500 Å). Accordingly, etching of the residual portion 111b of the silicon oxide film cannot be used. This eliminates the possibility of combining a salicide process which is the standard scheme of forming logic transistors with the fabrication method of the second prior art.